A Phase-Locked Loop (“PLL”) device is basically a closed loop frequency control system that compares the phase and frequency of two signals, a reference signal and a feedback signal, and produces an error signal that is proportional to the difference between these two signals. PLL circuits may be used in many applications, with the initial applications being in radio television receivers. With the development of low-cost integrated circuit (“IC”) packages, the PLL principle has been extended to many other applications, including PLL receivers capable of recovering low-level signals from satellites, AM and FM demodulators, FSK decoders, motor speed controls, isolators, and Radio Control receivers and transmitters.
Typically, a PLL may include a phase detector, a loop filter, and a voltage controlled oscillator (“VCO”) connected together in the form of a negative-feedback loop. FIG. 1 shows a simplified block diagram of an example of a conventional PLL circuit 100. The PLL circuit 100 may include a phase detector 102, loop filter 104, voltage controlled oscillator (“VCO”) 106, divider 108, and optional divide-by-M counter 110.
In an example of operation of the PLL circuit 100, the phase detector 102 compares the phase of two signals, a frequency reference input signal (“FIN”) 112 and a feedback signal 120, and, in response, generates a phase-error output signal 122 that is proportional to the difference between the input phases of FIN 112 and the feedback signal 120. The phase-error output signal 122 may be filtered and amplified in loop filter 104 to produce a filtered signal 124. The filtered signal 124 is input to the VCO 106 that adjusts an output signal (“FVCO”) 126 to satisfy the lock conditions of the PLL circuit 100.
The output signal FVCO 126 may be fed through the divider 108 (such as a Divide-by-N Counter) back to the phase detector 102. The Divide-by-N Counter 108 may be either an integer divider, in which case the locked VCO 106 is tuned to N-times the Phase Detector reference frequency 128, or a fractional divider, in which case the locked VCO 106 is tuned to N F-times the Phase Detector reference frequency 128. If the optional Divide-by-M Counter 110 is placed in the reference input, a divider circuit is created and the Phase Detector reference frequency 128 is a divide input signal 130 that equal to FIN 112 divided by M, and the output signal FVCO 126 is equal to N/M×FIN. In general, the phase-error signal 122 causes the VCO 106 frequency to track FIN by the ratio N/M.
In a common application of a PLL, a modulo-N counter (108) may be connected between the VCO 106 output and the phase detector 102 in the feedback path, thus generating a VCO 106 frequency FVCO 126 that is an integer multiple of the input reference frequency FIN 128. This is an ideal method for generating clocking pulses at a multiple of the power-line frequency for integrating A/D converters (dual-slope, charge-balancing), in order to have infinite rejection of interference at the power-line frequency and its harmonics. It also provides the basic technique of frequency synthesizers.
If conditions are right, the VCO 106 will quickly “lock” to FIN 128, maintaining a fixed relationship with the input reference signal FIN 128. Generally, there are two common methods to detect whether a PLL is locked, that is, the VCO 106 output tracks FIN 128: An analog method based on a window detector and a digital method based on a cycle-slip detector. In the analog method, the window detector (“WD”) typically monitors either the tune voltage (filtered signal 124) into the VCO 106 or the Phase-Frequency Detector 102 output voltage (phase-error signal 122). If these voltages exceed an expected range, the PLL 100 is most likely unlocked. However, because the window is typically set wide enough to accommodate design tolerances, it is possible for the PLL to sometimes be unlocked without causing the WD to detect the unlocked condition.
The cycle-slip detector (“CSD”) is a digital unlock detector that works on the simple principle that once the PLL is locked, there must be a cycle-for-cycle correspondence between the feedback signal and the input reference signal applied to the phase detector. Any deviation from the one-to-one cycle-for-cycle correspondence indicates a cycle-slipped condition, which is also an unlock condition for the PLL. Generally, a simple CSD may be constructed using flip-flops and logic gates.
Unfortunately, there are several problems that may occur when utilizing a CSD to determine when a PLL circuit locks. The first is transient false-lock detection, i.e., an indication that the circuit is locked when the circuit is, in fact, not locked, which may occur in a simple CSD without a counter. Transient false-lock detection may be greatly reduced by utilizing a lock counter that requires a specified number of locked cycles to occur before the unlock signal is de-asserted, i.e., the CSD is reset to the lock position. By adjusting the value of the lock counter, the closeness of the output frequency to the final frequency of the PLL when the unlock signal is de-asserted may be predetermined and specified. This is useful when the PLL frequency has to be hopped quickly, and the settling time for the PLL needs to be reduced to the greatest extent possible.
An additional problem is that the two input signals to the CSD must be phase offset to avoid simultaneous clocking. At high input frequencies, the phase adjustment becomes more critical since the variation of the differential delay of the two signals can approach a significant portion of the reference period. This problem is aggravated when fractional division implemented with dithering is used, further reducing the window of allowable phase offset. The phase offset can always be manually adjusted to work over a limited range of reference frequency if the signal delay is fixed. When the reference frequency has to be changed over a substantial range, however, re-adjustment of the phase offset is needed. The adaptive phase shifter may be used to eliminate the manual phase offset adjustment, ensuring optimal margin over a wide range of reference frequency.
Therefore, there is a need for a CSD with an adaptive phase shifter that automatically positions the active edges of the input signals to the CSD to provide symmetrical unlock detection and thus maximum margin for accommodating dithered signals produced through fractional division, and that also has a lock counter that eliminates transient false lock indications by requiring a specified consecutive number of signal periods to occur before the CSD output can be reset to the lock position.